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general description the max5945 quad network power controller is designed for use in ieee 802.3af-compliant power-sourcing equip- ment (pse). the device provides power devices (pd) dis- covery, classification, current-limit, and both dc and ac load disconnect detections. the max5945 can be used in either endpoint pse (lan switches/routers) or midspan pse (power injector) applications. the max5945 is pin and function compatible with ltc4259a. the max5945 can operate autonomously or be con- trolled by software through an i 2 c*-compatible inter- face. separate input and output data lines (sdain and sdaout) allow usage with optocouplers. the max5945 is a slave device. its four address inputs allow 16 unique max5945 addresses. a separate int output and four independent shutdown inputs ( shd_ ) allow fast response from a fault to port shutdown. a reset input allows hardware reset of the device. a special watchdog feature allows the hardware to grace- fully take over control if the software crashes. a cadence timing feature allows the max5945 to be used in midspan systems. the max5945 is fully software configurable and program- mable. a class-overcurrent detection function enables system power management to detect if a pd draws more current than the allowable amount for its class. other fea- tures are input under/overvoltage lockout, overtempera- ture protection, output-voltage slew-rate limit during startup, power-good, and fault status. the max5945? programmability includes gate-charging current, current- limit threshold, startup timeout, overcurrent timeout, autorestart duty cycle, pd disconnect ac detection threshold, and pd disconnect detection timeout. the max5945 is available in a 36-pin ssop package and is rated for both extended (-40? to +85?) and commercial (0? to +70?) temperature ranges. applications power-sourcing equipment (pse) power-over-lan/power-over-ethernet switches/routers midspan power injectors features ? ieee 802.3af compliant ? pin and function compatible with ltc4259a ? controls four independent, -48v-powered ethernet ports in either endpoint or midspan pse applications ? wide digital power input, v dig , common-mode range: v ee to (agnd + 7.7v) ? pd violation of class current protection ? pd detection and classification ? provides both dc and ac load removal detections ? i 2 c-compatible, 3-wire serial interface ? fully programmable and configurable operation through i 2 c interface ? current foldback and duty-cycle- controlled/programmable current limit ? short-circuit protection with fast gate pulldown ? direct fast shutdown control capability ? programmable direct interrupt output ? watchdog mode enable hardware graceful takeover max5945 quad network power controller for power-over-lan ________________________________________________________________ maxim integrated products 1 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 osc_in auto out1 gate1 sense1 out2 gate4 gate2 sense2 v ee out3 gate3 sense3 out4 det4 det3 det2 det1 a0 a1 a2 a3 sdain sdaout scl midspan ssop top view max5945 22 21 20 19 15 16 17 18 sense4 agnd v dd dgnd reset int shd1 shd2 shd3 shd4 pin configuration 19-3428; rev 1; 9/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available ordering information part temp range pin-package max5945cax** 0? to +70? 36 ssop max5945eax -40? to +85? 36 ssop * purchase of i 2 c components from maxim integrated products, inc. or one of its sublicensed associated companies, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ** future product?ontact factory for availability. typical operating circuits appear at end of data sheet.
max5945 quad network power controller for power-over-lan 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltages referenced to v ee , unless otherwise noted.) agnd, dgnd, det_, v dd , reset , a3, a2, a1, a0, shd_ , osc_in, scl, sdain, out_ and auto............-0.3v to +80v gate_ (internally clamped, note 1)....................-0.3v to +11.4v sense_ ..................................................................-0.3v to +24v v dd , reset , a3, a2, a1, a0, shd_ , osc_in, scl, sdain and auto to dgnd ....................................................-0.3v to +7v int and sdaout to dgnd....................................-0.3v to +12v maximum current into int , sdaout, det_ .......................80ma maximum power dissipation 36-pin ssop (derate 11.4mw/? above +70?) .........941mw operating temperature ranges: max5945eax ..................................................-40? to +85? max5945cax .....................................................0? to +70? storage temperature range .............................-65? to +150? junction temperature ......................................................+150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (agnd = +32v to +60v, v ee = 0v, v dd to dgnd = +3.3v, all voltages are referenced to v ee , unless otherwise noted. typical values are at agnd = +48v, dgnd = +48v, v dd = (dgnd + 3.3v), t a = +25?. currents are positive when entering the pin and negative otherwise.) parameter symbol conditions min typ max units power supplies v agnd v agnd - v ee 32 60 v dgnd 060 v dd to v dgnd , v dgnd = v agnd 1.71 5.50 operating voltage range v dd v dd to v dgnd , v dgnd = v ee 3.0 5.5 v i ee out_ = v ee , sense_ = v ee , det_ = agnd, all logic inputs open, scl = sdain = v dd , int and sdaout open; measured at agnd in power mode after gate_ pullup 4.2 6.8 supply currents i dig all logic inputs high, measured at v dd 2.7 5.6 ma gate driver and clamping gate_ pullup current i pu power mode, gate drive on, v gate = v ee (note 2) -40 -50 -60 a weak gate_ pulldown current i pdw shd_ = dgnd, v gate_ = v ee + 5v 30 40 50 ? maximum pulldown current i pds v sense = 1v, v gate_ = v ee + 2v 100 ma external gate drive v gs v gate - v ee , power mode, gate drive on 9 10 11 v current limit current-limit clamp voltage v su_lim maximum v sense_ allowed during current limit, v out_ = v ee (note 3) 202 212 220 mv default, class 0, class 3, class 4 178.5 196 class 1 49 61 overcurrent threshold after startup v flt_lim overcurrent v sense_ threshold allowed for t t fault after startup; v out_ = v ee class 2 90 104 mv foldback initial out_ voltage v flbk_st v out_ - v ee , above which the current-limit trip voltage starts folding back 30 v foldback final out_ voltage v flbk_end v out_ - v ee , above which the current-limit trip voltage reaches v th_fb 50 v note 1: gate_ is internally clamped to 11.4v above v ee . driving gate_ higher than 11.4v above v ee may damage the device.
max5945 quad network power controller for power-over-lan _______________________________________________________________________________________ 3 electrical characteristics (continued) (agnd = +32v to +60v, v ee = 0v, v dd to dgnd = +3.3v, all voltages are referenced to v ee , unless otherwise noted. typical values are at agnd = +48v, dgnd = +48v, v dd = (dgnd + 3.3v), t a = +25?. currents are positive when entering the pin and negative otherwise.) parameter symbol conditions min typ max units minimum foldback current- limit threshold v th_fb v out_ = v agnd 64 mv sense_ input bias current v sense_ = v ee -2 ? supply monitors v ee undervoltage lockout v eeuvlo v agnd - v ee , (v agnd - v ee ) increasing 27 28.5 30 v v ee undervoltage-lockout hysteresis v eeuvloh 3v v ee overvoltage v ee_ov (v agnd - v ee ) > v ee_ov , v agnd increasing 61 62.5 64 v v ee overvoltage hysteresis v ovh 1v v ee undervoltage v ee_uv (v agnd - v ee ) < v ee_uv , v agnd decreasing 39 40 41 v v dd overvoltage v dd_ov (v dd - v dgnd ) > v dd_ov , v dd increasing 3.57 3.71 3.90 v v dd undervoltage v dd_uv (v dd - v dgnd ) < v dd_uv , v dd decreasing 2.55 2.82 2.97 v v dd undervoltage lockout v dduvlo device operates when (v dd - v dgnd ) > v dduvlo , v dd increasing 1.7 v v dd undervoltage-lockout hysteresis v ddhys 120 mv thermal-shutdown threshold t shd ports shut down and device resets if its junction temperature exceeds this limit, temperature increasing +150 ? thermal-shutdown hysteresis t shdh 20 ? output monitor out_ input current i bout v out = v agnd , all modes 2 a idle pullup current at out_ i dis out_ discharge current, detection and classification off, port shutdown, v out_ = v agnd - 2.8v 200 260 ? pgood high threshold pg th v out_ - v ee , out_ decreasing 1.8 2.0 2.2 v pgood hysteresis pg hys 220 mv pgood low-to-high glitch filter t pgood minimum time pgood has to be high to set bit in register 10h 24ms load disconnect dc load disconnect threshold v dcth minimum v sense allowed before disconnect (dc disconnect active), v out_ = v ee 345mv
max5945 quad network power controller for power-over-lan 4 _______________________________________________________________________________________ electrical characteristics (continued) (agnd = +32v to +60v, v ee = 0v, v dd to dgnd = +3.3v, all voltages are referenced to v ee , unless otherwise noted. typical values are at agnd = +48v, dgnd = +48v, v dd = (dgnd + 3.3v), t a = +25?. currents are positive when entering the pin and negative otherwise.) parameter symbol conditions min typ max units ac load disconnect threshold (note 4) i acth current into det_, acd_en_ bit = high, osc_in = 2.2v 300 325 350 ? oscillator buffer gain a osc v det_ / v osc_in , acd_en_ bit = high, c det = 400nf 2.92 2.98 3.04 v/v osc_in fail threshold (note 5) v os c _f ai l port will not power on if v osc_in < v osc_fail and acd_en_ bit = high 1.8 1.9 2.1 v osc_in input resistance z osc osc_in input impedance when all the acd_en_ are active 100 k ? osc_in input capacitance c osc_in 5pf load disconnect timer t disc time from v sense < v dcth or current into det_ < i acth to gate shutdown (note 6) 300 400 ms detection detection probe voltage (first phase) v dph1 v agnd - v det_ during the first detection phase 3.8 4 4.2 v detection probe voltage (second phase) v dph2 v agnd - v det_ during the second detection phase 9.0 9.3 9.6 v current-limit protection i dlim v det_ = v agnd , during detection, measure current through det_ 1.5 1.75 2.0 ma short-circuit threshold v dcp if v a gn d - v ou t < v d c p after the fi r st d etecti on p hase a shor t ci r cui t to ag n d i s d etected 1.62 v open-circuit threshold i d_open first point measurement current threshold for open condition 12.5 ? resistor detection window r dok (note 7) 18.6 26.5 k ? detection rejects lower values 16 resistor rejection window r dbad detection rejects higher values 30 k ? classification classification probe voltage v cl v agnd - v det_ during classification 16 20 v current-limit protection i cllim v det_ = v agnd , during classification, measure current through det_ 50 75 ma class 0, class 1 5.5 6.5 7.5 class 1, class 2 13.5 14.5 15.5 class 2, class 3 21.5 23 24.5 class 3, class 4 31 33 35 classification current thresholds i cl classification current thresholds between classes >class 4 45 48 51 ma digital inputs/outputs (referred to dgnd) digital input low v il 0.9 v digital input high v ih 2.4 v
max5945 quad network power controller for power-over-lan _______________________________________________________________________________________ 5 electrical characteristics (continued) (agnd = +32v to +60v, v ee = 0v, v dd to dgnd = +3.3v, all voltages are referenced to v ee , unless otherwise noted. typical values are at agnd = +48v, dgnd = +48v, v dd = (dgnd + 3.3v), t a = +25?. currents are positive when entering the pin and negative otherwise.) parameter symbol conditions min typ max units internal input pullup/pulldown resistor r din pullup (pulldown) resistor to v dd (dgnd) to set default level 25 50 75 k ? open-drain output low voltage v ol i sink = 15ma 0.4 v open-drain leakage i ol open-drain high impedance, v o = 3.3v 2 a timing startup time t start time during which a current limit set by v su_lim is allowed, starts when the gate_ is turned on (note 8) 50 60 70 ms fault time t fault maximum allowed time for an overcurrent condition set by v flt_lim after startup (note 8) 50 60 70 ms port turn-off time t off minimum delay between any port turning off, does not apply in the case of a reset 0.5 0.75 1.0 ms detection time t det maximum time allowed before detection is completed 320 ms midspan mode detection delay t dmid 2.0 2.4 s classification time t class time allowed for classification 40 ms v eeuvlo turn-on delay t dly time v agnd must be above the v eeuvlo thresholds before the device operates 24ms rstr bits = 00 16 x t fault rstr bits = 01 32 x t fault rstr bits = 10 64 x t fault restart timer t restart ti m e a p or t has to w ai t b efor e tur ni ng on after an over cur r ent faul t, rs tr_e n b i t = hi g h rstr bits = 11 0 ms watchdog clock period t wd rate of decrement of the watchdog timer 164 ms timing characteristics for 2-wire fast mode (figures 5 and 6) serial clock frequency f scl (note 9) 400 khz bus free time between a stop and a start condition t buf (note 9) 1.2 ? hold time for start condition t hd , sta (note 9) 0.6 ? low period of the scl clock t low (note 9) 1.2 ? high period of the scl clock t high (note 9) 0.6 ?
max5945 quad network power controller for power-over-lan 6 _______________________________________________________________________________________ note 2: default values. the charge/discharge currents are programmable through the serial interface (see the register map and description section). note 3: default values. the current-limit thresholds are programmed through the i 2 c-compatible serial interface (see the register map and description section). note 4: this is the default value. threshold can be programmed through serial interface r23h[2:0]. note 5: ac disconnect works only if v dd - v dgnd 3v. note 6: t disc can also be programmed through the serial interface (r29h) (see the register map and description section). note 7: r d = (v out_2 - v out_1 ) / (i det_2 - i det_1 ). v out_1 , v out_2 , i det_2 and i det_1 represent the voltage at out_ and the current at det_ during phase 1 and 2 of the detection. note 8: default values. the startup and fault times can also be programmed through the i 2 c serial interface (see the register map and description section). note 9: guaranteed by design. not subject to production testing. analog supply current vs. input voltage max5945 toc01 input voltage (v) supply current (ma) 57 52 47 42 37 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 3.5 32 62 measured at agnd analog supply current vs. temperature max5945 toc02 temperature ( c) supply current (ma) 60 35 10 -15 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 3.0 -40 85 digital supply current vs. temperature max5945 toc03 temperature ( c) supply current (ma) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 -40 85 typical operating characteristics (v ee = -48v, v dd = +3.3v, auto = agnd = dgnd = 0v, reset = shd_ = unconnected, r sense = 0.5 ? , all registers = default setting, t a = +25?, unless otherwise noted.) electrical characteristics (continued) (agnd = +32v to +60v, v ee = 0v, v dd to dgnd = +3.3v, all voltages are referenced to v ee , unless otherwise noted. typical values are at agnd = +48v, dgnd = +48v, v dd = (dgnd + 3.3v), t a = +25?. currents are positive when entering the pin and negative otherwise.) parameter symbol conditions min typ max units setup time for a repeated start condition (sr) t su , sta (note 9) 0.6 ? data hold time t hd , dat (note 9) 0 150 ns data setup time t su , dat (note 9) 100 ns rise time of both sda and scl signals, receiving t r (note 9) 20 + 0.1c b 300 ns fall time of sda transmitting t f (note 9) 20 + 0.1c b 300 ns setup time for stop condition t su , sto (note 9) 0.6 ? c ap aci ti ve load for e ach bus li ne c b (note 9) 400 pf pulse width of spike suppressed t sp (note 9) 50 ns
max5945 quad network power controller for power-over-lan _______________________________________________________________________________________ 7 digital supply current vs. input voltage max5945 toc04 input voltage (v) supply current (ma) 4.6 4.2 3.8 3.4 3.0 2.6 2.2 1 2 3 4 5 6 0 1.8 5.0 measured at v dd v ee undervoltage lockout vs. temperature max5945 toc05 temperature ( c) undervoltage lockout (v) 60 35 10 -15 27.5 28.0 28.5 29.0 29.5 30.0 27.0 -40 85 gate overdrive vs. input voltage max5945 toc06 input voltage (v) gate overdrive (v) 57 52 47 42 37 9.80 9.82 9.84 9.86 9.88 9.90 9.92 9.94 9.96 9.98 9.78 32 62 gate overdrive vs. temperature max5945 toc07 temperature ( c) gate overdrive (v) 60 35 10 -15 9.6 9.7 9.8 9.9 10.0 10.1 10.2 10.3 10.4 10.5 9.5 -40 85 sense trip voltage vs. temperature max5945 toc08 temperature ( c) sense trip voltage (mv) 60 35 10 -15 175 180 185 190 195 200 170 -40 85 sense trip voltage vs. input voltage max5945 toc09 input voltage (v) sense trip voltage (mv) 57 52 47 42 37 182 184 186 188 190 180 32 62 foldback current-limit threshold vs. output voltage max5945 toc10 v out - v ee (v) v sense - v ee (mv) 40 30 20 10 50 100 150 200 250 300 0 050 zero-current detection threshold vs. temperature max5945 toc11 temperature ( c) detection threshold (mv) 60 35 10 -15 1 2 3 4 5 0 -40 85 typical operating characteristics (continued) (v ee = -48v, v dd = +3.3v, auto = agnd = dgnd = 0v, reset = shd_ = unconnected, r sense = 0.5 ? , all registers = default setting, t a = +25?, unless otherwise noted.)
max5945 quad network power controller for power-over-lan 8 _______________________________________________________________________________________ overcurrent timeout (r load = 240 ? to 57 ? ) max5945 toc12 20ms/div 0v i out 200ma/div v ee gate 10v/div 0a int 2v/div (agnd - out) 20v/div 0v overcurrent response waveform (r load = 240 ? to 57 ? ) max5945 toc13 400 s/div 0v i out 200ma/div gate 10v/div v ee 0a int 2v/div (agnd - out) 20v/div 0v short-circuit response time max5945 toc14 20ms/div 0v i out 250ma/div gate 10v/div v ee 0a (agnd - out) 20v/div short-circuit response time max5945 toc15 4 s/div 0v i out 5a/div gate 10v/div v ee 0a (agnd - out) 20v/div reset to output turn-off delay max5945 toc16 100 s/div 0v i out 200ma/div gate 10v/div v ee 0a reset (agnd - out) 20v/div zero-current detection waveform max5945 toc17 100ms/div 0v i out 200ma/div gate 10v/div int 5v/div (agnd - out) 20v/div typical operating characteristics (continued) (v ee = -48v, v dd = +3.3v, auto = agnd = dgnd = 0v, reset = shd_ = unconnected, r sense = 0.5 ? , all registers = default setting, t a = +25?, unless otherwise noted.)
max5945 quad network power controller for power-over-lan _______________________________________________________________________________________ 9 overcurrent restart delay max5945 toc18 400ms/div 0v 0a i out 200ma/div gate 10v/div v ee (agnd - out) 20v/div startup with valid pd (25k ? and 0.1 f) max5945 toc19 100ms/div 0v i out 100ma/div gate_ v ee (agnd - out) 20v/div detection with invalid pd (25k ? and 10 f) max5945 toc20 40ms/div 0v i out 1ma/div (agnd - out) 2v/div detection with invalid pd (15k ? ) max5945 toc21 100ms/div 0v 0a i out 1ma/div (agnd - out) 5v/div detection with invalid pd (33k ? ) max5945 toc22 100ms/div 0v 0a i out 1ma/div (agnd - out) 5v/div startup in midspan mode with valid pd (25k ? and 0.1 f) max5945 toc23 100ms/div 0v 0a i out 100ma/div v ee gate_ 10v/div (agnd - out) 20v/div typical operating characteristics (continued) (v ee = -48v, v dd = +3.3v, auto = agnd = dgnd = 0v, reset = shd_ = unconnected, r sense = 0.5 ? , all registers = default setting, t a = +25?, unless otherwise noted.)
max5945 quad network power controller for power-over-lan 10 ______________________________________________________________________________________ detection with midspan mode with invalid pd (15k ? ) max5945 toc24 400ms/div 0v 0a i out 1ma/div v ee gate_ 10v/div (agnd - out) 5v/div detection with midspan mode with invalid pd (33k ? ) max5945 toc25 400ms/div 0v 0a i out 1ma/div v ee gate_ 10v/div (agnd - out) 5v/div detection with output shorted max5945 toc26 40ms/div 0v 0a i out 1ma/div v ee gate_ 10v/div (agnd - out) 5v/div detection with invalid pd (open circuit, using typical operating circuit 1) max5945 toc27 100ms/div 0a 0v i out 1ma/div v ee gate_ 10v/div (agnd - out) 5v/div detection with invalid pd (open circuit, using typical operating circuit 2) max5945 toc28 100ms/div i out 2ma/div 0v gate_ 10v/div (agnd - out) 5v/div startup with different pd classes max5945 toc29 40ms/div i out 10ma/div (agnd - out) 5v/div class0 class1 class2 class3 class4 typical operating characteristics (continued) (v ee = -48v, v dd = +3.3v, auto = agnd = dgnd = 0v, reset = shd_ = unconnected, r sense = 0.5 ? , all registers = default setting, t a = +25?, unless otherwise noted.)
max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 11 pin name function 1 reset hardware reset. pull reset low for at least 300? to reset the device. all internal registers reset to their default value. the address (a0?3), and auto and midspan input logic levels latch on during low-to-high transition of reset . internally pulled up to v dd with 50k ? resistor. 2 midspan midspan mode input. an internal 50k ? pulldown resistor to dgnd sets the default mode to endpoint pse operation (power-over-signal pairs). pull midspan to v dig to set midspan operation. the midspan value latches after the ic is powered up or reset (see the pd detection section). 3 int open-drain interrupt output. int goes low whenever a fault condition exists. reset the fault condition using software or by pulling reset low (see the interrupt section of the detailed description for more information about interrupt management). 4 scl serial interface clock line 5 sdaout serial output data line. connect the data line optocoupler input to sdaout (see the typical application circuit ). connect sdaout to sdain if using a 2-wire i 2 c-compatible system. 6 sdain serial interface input data line. connect the data line optocoupler output sdain (see the typical application circuit ). connect sdain to sdaout if using a 2-wire wire i 2 c-compatible system. 7?0 a3, a2, a1, a0 address bits. a3, a2, a1, and a0 form the lower part of the device? address. address inputs default high with an internal 50k ? pullup resistor to v dd . the address values latch when v dd or v ee ramps up and exceeds its uvlo threshold or after a reset. the 3 msb bits of the address are set to 010. 11?4 det1, det2, det3, det4 detection and classification voltage outputs. use det1 to set the detection and classification probe voltages on port 1. use det1 for the ac voltage sensing of port 1 when using the ac disconnect scheme (see the typical application circuit ). 15 dgnd connect to digital ground 16 v dd positive digital supply. connect to digital supply (referenced to dgnd). 17?0 shd1 , shd2 , shd3 , shd4 port shutdown inputs. pull shd_ low to turn off the external fet on port_. internally pulled up to v dd with a 50k ? resistor. 21 agnd analog ground. connect to the high-side analog supply. 22, 25, 29, 32 sense4, sense3, sense2, sense1 mosfet source current-sense negative inputs. connect to the source of the power mosfet and connect a current-sense resistor between sense_ and v ee (see the typical application circuit ). 23, 26, 30, 33 gate4, gate3, gate2, gate1 port_ mosfet gate drivers. connect gate_ to the gate of the external fet (see the typical application circuit ). 24, 27, 31, 34 out4, out3, out2, out1 mosfet drain-output voltage senses. connect out_ to the power mosfet drain through a resistor (100 ? to 100k ? ). the low leakage at out_ limits the drop across the resistor to less than 100mv (see the typical application circuit ). 28 v ee low-side analog supply input. connect the low-side analog supply to v ee (-48v). bypass with a 1? capacitor between agnd and v ee . 35 auto auto or shutdown mode input. force high to enter auto mode after a reset or power-up. drive low to put the max5945 into shutdown mode. in shutdown mode, software controls the operational modes of the max5945. a 50k ? internal pulldown resistor defaults auto low. auto latches when v dd or v ee ramps up and exceeds its uvlo threshold or when the device resets. software commands can take the max5945 out of auto while auto is high. 36 osc_in oscillator input. ac-disconnect detection function uses osc_in. connect a 100hz ?0%, 2v p-p ?%, +1.2v offset sine wave to osc_in. if the oscillator positive peak falls below the osc_fail threshold of 2v, the ports that have the ac function enabled shut down and are not allowed to power up. when not using the ac-disconnect detection function, leave osc_in unconnected. pin description
max5945 detailed description the max5945 four-port network power controller con- trols -32v to -60v negative supply rail systems. use the max5945, which is compliant with the ieee 802.3af standard for pse in power-over-lan applications. the max5945 provides pd discovery, classification, current limit, both dc and ac load disconnect detections, and other necessary functions for an ieee 802.3af-compli- ant pse. the max5945 can be used in either endpoint pse (lan switch/router) or midspan pse (power injec- tor) applications. the max5945 is fully software-configurable and pro- grammable with more than 25 internal registers. the device features an i 2 c-compatible, 3-wire serial inter- face and a class-overcurrent detection. the class-over- current detection function enables system power man- quad network power controller for power-over-lan 12 ______________________________________________________________________________________ 50 a 90 a 100ma max fast discharge control 212mv 182mv 13v clamp current-limit detector 4mv overcurrent (ovc) open circuit (oc) current limit (ilim) pwr_en 10v voltage sensing foldback control 9-bit adc converter voltage probing and current-limit control current sensing sense_ gate_ out_ det_ a = 3 ac detection acd_enable ac disconnect signal (acd) acd reference current detection/ classification sm port state machine (sm) register file serial port interface (spi) auto midspan a0 a1 a2 a3 analog bias/ supply monitor agnd v ee +10v analog +5v dig voltage references current references central logic unit (clu) dgnd osc_in scl sdain sdaout v dd oscillator monitor shd_ reset int max5945 figure 1. max5945 functional diagram
agement where it detects a pd that draws more current than the allowable amount for its class. the max5945? extensive programmability enhances system flexibility and allows for uses in other applications. the max5945 has four different operating modes: auto mode, semi-auto mode, manual mode, and shutdown mode (see the operation modes section). a special watchdog feature allows the hardware to gracefully take over control if the software/firmware crashes. a cadence timing feature allows the max5945 to be used in midspan systems. the max5945 provides input undervoltage lockout, input undervoltage detection, input overvoltage lockout, overtemperature protection, output-voltage slew-rate limit during startup, power-good status, and fault status. the max5945? programmability includes gate-charging current, current-limit threshold, startup timeout, overcurrent timeout, autorestart duty cycle, pd disconnect ac detection threshold and pd disconnect detection timeout. the max5945 communicates with the system microcontroller through an i 2 c-compatible interface. the max5945 features separate input and output data lines (sdain and sdaout) for use with optocoupler isolation. the max5945 is a slave device. its four address inputs allow 16 unique max5945 addresses. a separate int output and four independent shutdown inputs ( shd_ ) allow fast interrupt signals between the max5945 and the microcontroller. a reset input allows hardware reset of the device. reset reset is a condition the max5945 enters after any of the following conditions: after power-up (v ee and v dd rise above their uvlo thresholds). hardware reset. the reset input is driven low and up high again any time after power-up. software reset. writing a 1 into r1ah[4] any time after power-up. thermal shutdown. during a reset, the max5945 resets its register map to the reset state as shown in table 30 and latches in the state of auto (pin 35) and midspan (pin 2). during normal operation, changes at the auto and midspan inputs are ignored. while the condition that caused the reset persists (i.e., high temperature, reset input low, or uvlo conditions) the max5945 will not acknowl- edge any addressing from the serial interface. port reset (r1ah[3:0]) set high anytime during normal operation to turn off power and clear the events and status registers of the corresponding port. port reset only resets the events and status registers. operation modes the max5945 contains four independent but identical state machines to provide reliable and real-time control of the four network ports. each state machine has four different operating modes: auto, semi-auto, manual, and shutdown. auto mode allows the device to operate automatically without any software supervision. semi- auto mode, upon request, continuously detects and classifies a device connected to a port but does not power up that port until instructed by software. manual mode allows total software control of the device and is useful in system diagnostic. shutdown mode terminates all activities and securely turns off power to the ports. switching between auto, semi, or manual mode does not take effect until the part finishes its current task. when the port is set into shutdown mode, all the port operations are immediately stopped and the port remains idle until shutdown is exited. automatic (auto) mode enter automatic (auto) mode by forcing the auto input high prior to a reset, or by setting r12h[p_ m1,p_m0] to [1,1] during normal operation (see tables 15 and 15a). in auto mode, the max5945 performs detection, classification, and powers up the port automatically once a valid pd is detected at the port. if a valid pd is not detected at the port, the max5945 repeats the detection routine continuously until a valid pd is detected. going into auto mode, the det_en and class_en bits are set to high and stay high unless changed by software. using software to set det_en and/or class_en low causes the max5945 to skip detection and/or classification. as a protection, disabling the detection routine in auto mode will not allow the corre- sponding port to power up, unless the det_byp (r23h[4]) is set to 1. the auto status is latched into the register only during a reset. any changes to the auto input after reset is ignored. semi-automatic (semi) mode enter semi-automatic (semi) mode by setting r12h[p_m1,p_m0] to [1,0] during normal operation (see tables 15 and 15a). in semi mode, the max5945, upon request, performs detection and/or classification repeatedly but does not power up the port(s), regard- less of the status of the port connection. max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 13
max5945 setting r19h[pwr_on_] (table 21) high immediately terminates detection/classification routines and turns on power to the port(s). r14h[det_en_, class_en_] default to low in semi mode. use software to set r14h[det_en_, class_en_] to high to start the detection and/or classi- fication routines. r14h[det_en_, class_en_] are reset every time the software commands a power-off of the port (either through reset or pwr_off). in any other case, the status of the bits is left unchanged (including when the state machine turns off the power because a load disconnect or a fault condition is encountered). manual mode enter manual mode by setting r12h[p_m1,p_m0] to [0,1] during normal operation (see tables 15 and 15a). manual mode allows the software to dictate any sequence of operation. write a 1 to both r14h[det_ en_] and r14h[class_en_] start detection and classifica- tion operations, respectively, and in that priority order. after execution, the command is cleared from the regis- ter(s). pwr_on_ has highest priority. setting pwr_on_ high at any time causes the device to immediately enter the powered mode. setting det_en and class_en high at the same time causes detection to be per- formed first. once in the powered state, the device ignores det_en_ or class_en_ commands. when switching to manual mode from another mode, det_en_, class_en_ default to low. these bits become pushbutton rather than configuration bits (i.e., writing ones to these bits while in manual mode com- mands the device to execute one cycle of detection and/or classification. the bits are reset back to zeros at the end of the execution). putting the max5945 into shutdown mode immediately turns off power and halts all operations to the corresponding port. the event and status bits of the affected port(s) are also cleared. in shutdown mode, the det_en_, class_en_, and pwr_on_ commands are ignored. in shutdown mode, the serial interface operates normally. watchdog r1dh, r1eh, and r1fh registers control watchdog oper- ation. the watchdog function, when enabled, allows the max5945 to gracefully take over control or securely shut down the power to the ports in case of software/firmware crashes. contact the factory for more details. pd detection when pd detection is activated, the max5945 probes the output for a valid pd. after each detection cycle, the device sets the det_end_ bit r04h/05h[3:0] high and reports the detection results in the status registers r0ch[2:0], r0dh[2:0], r0eh[2:0], and r0fh[2:0]. the det_end_ bit is reset to low when read through r05h or after a port reset. both det_end_ bit status registers are cleared after the port powers down. a valid pd has a 25k ? discovery signature characteris- tic as specified in the ieee 802.3af standard. table 1 shows the ieee 802.3af specification for a pse detect- ing a valid pd signature (see the typical application circuit and figure 2). the max5945 can probe and cat- egorize different types of devices connected to the port such as a valid pd, an open circuit, a low resistive load, a high resistive load, a high capacitive load, a positive dc supply, or a negative dc supply. during detection, the max5945 turns off the external mosfet and forces two probe voltages through the det_ input. the current through the det_ input is mea- sured as well as the voltage at out_. a two-point slope measurement is used as specified by the ieee 802.3af standard to verify the device connected to the port. the max5945 implements appropriate settling times and a 100ms digital integration to reject 50hz/60hz power- line noise coupling. an external diode, in series with the det_ input, restricts pd detection to the 1st quadrant as specified by the ieee 802.3af standard. to prevent damage to non-pd devices and to protect itself from an output short circuit, the max5945 limits the current into det_ to less than 2ma maximum during pd detection. in midspan mode, the max5945 waits 2.2s before attempting another detection cycle after every failed detection. the first detection, however, happens imme- diately after issuing the detection command. power device classification (pd classification) during the pd classification mode, the max5945 forces a probe voltage (-18v) at det_ and measures the cur- rent into det_. the measured current determines the class of the pd. after each classification cycle, the device sets the cl_end_ bit (r04h/05h[7:4]) high and reports the clas- sification results in the status registers r0ch[6:4], r0dh[6:4], r0eh[6:4], and r0fh[6:4]. the cl_end_ bit is reset to low when read through register r05h or after a port reset. both cl_end_ bit status registers are cleared after the port powers down. quad network power controller for power-over-lan 14 ______________________________________________________________________________________
table 2 shows the ieee 802.3af requirement for a pse classifying a pd at the power interface (pi). powered state when the part enters pwr mode, the t start and t disc timers are reset. before turning on the power, the part checks if any other port is not turning on and if the t fault timer is zero. another check is performed if the acd_en bit is set, in this case osc_fail bit must be low (oscillator is okay) for the port to be powered. if these conditions are met then the part enters startup where it turns on power to the port. an internal signal, pok_, is asserted high when v out is within 2v from v ee . pgood_ status bits are set high if pok_ stays high longer than t pgood . pgood immediately resets when pok goes low. the pwr_chg bit sets when a port powers up or down. pwr_en sets when a port powers up and resets when a port shuts down. the port shutdown timer lasts 0.5ms and prevents other ports from turning off during that peri- od, except in the case of emergency shutdowns ( reset = l, reset_ic = h, v eeuvlo , v dduvlo , and tshd). the max5945 always checks the status of all ports before turning off. a priority logic system determines the order to prevent the simultaneous turn-on or turn-off of the ports. the port with the lesser ordinal number gets priority over the others (i.e., port 1 turns on first, port 2 second, port 3 third and port 4 fourth). setting pwr_off_ high turns off power to the corresponding port. max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 15 parameter symbol min max units additional information open-circuit voltage v oc 30 v in detection mode only short-circuit current i sc 5 ma in detection mode only valid test voltage v valid 2.8 10 v voltage difference between test points ? v test 1v time between any two test points t bp 2 ms this timing implies a 500hz maximum probing frequency slew rate v slew 0.1 v/? accept signature resistance r good 19 26.5 k ? ? open-circuit resistance r open 500 ? ? accept signature capacitance c good 150 nf reject signature capacitance c bad 10 f signature offset voltage tolerance v os 0 2.0 v signature offset current tolerance i os 012a table 1. pse pi detection modes electrical requirement (table 33-2 of the ieee 802.3af standard) measured i class (ma) classification 0 to 5 class 0 > 5 and < 8 may be class 0 and 1 8 to 13 class 1 > 13 and < 16 may be class 0, 1, or 2 16 to 21 class 2 > 21 and < 25 may be class 0, 2, or 3 25 to 31 class 3 > 31 and <35 may be class 0, 3, or 4 35 to 45 class 4 > 45 and < 51 may be class 0 or 4 table 2. pse classification of a pd (table 33-4 of the ieee 802.3af standard)
max5945 overcurrent protection a sense resistor (r s ), connected between sense_ and v ee , monitors the load current. under all circum- stances, the voltage across r s never exceeds the threshold v su_lim . if sense_ exceeds v su_lim , an internal current-limiting circuit regulates the gate volt- age, limiting the current to i lim = v su_lim / r s . during transient conditions, if the sense_ voltage exceeds v su_lim , a fast pulldown circuit activates to quickly recover from the current overshoot. during startup, if the current-limit condition persists, when the startup timer, t start , times out, the port shuts off and the strt_flt_ bit is set. in normal powered state, the max5945 checks for overcurrent conditions as deter- mined by v flt_lim = ~88% of v su_lim . the t fault counter sets the maximum allowed continuous overcurrent period. the t fault counter increases when v sense exceeds v flt_lim and decreases at a slower pace when v sense drops below v flt_lim . a slower decrement for the t fault counter allows for detecting repeated short-duration overcurrents. when the counter reaches the t fault limit, the max5945 powers off the port and asserts the imax_flt_ bit. for a continuous overstress, a fault latches exactly after a period of t fault . v su_lim , is programmable using r27h[4-7]. t fault is programmable using r16h[2-3] and r28[4-7]. after power-off due to an overcurrent fault, and if the rstr_en bit is set, the t fault timer is not immediately reset but starts decrementing at the same slower pace. the max5945 allows the port to be powered on only when the t fault counter is at zero. this feature sets an automatic duty-cycle protection to the external mosfet to avoid overheating. the duty cycle is programmable using r16h[6-7]. the max5945 continuously flags when the current exceeds the maximum current allowed for the class as indicated in the class status register. when class overcurrent occurs, the max5945 sets the ivc bit in register r09h. foldback current during startup and normal operation, an internal circuit senses the voltage at out_ and reduces the current- limit value when (v out _ - v ee ) > 30v. the foldback function helps to reduce the power dissipation on the fet. the current limit eventually reduces to 1/3 of i lim when (v out _ - v ee ) > 50v (see figure 4). quad network power controller for power-over-lan 16 ______________________________________________________________________________________ figure 2. detection, classification, and power-up port sequence out_ -4v -9v -18v -48v t t deti t detii t class 150ms 150ms 21.3ms 0v 0v 80ms figure 3. pgood timing pgood pok t pgood
mosfet gate driver connect the gate of the external n-channel mosfet to gate_. an internal 50? current source pulls gate_ to (v ee + 10v) to turn on the mosfet. an internal 40? current source pulls down gate_ to v ee to turn off the mosfet. the pullup and pulldown current controls the maximum slew rate at the output during turn-on or turn-off. the pullup current (gate-charging current) is programmable using r23h[5-7]. use the following equation to set the maximum slew rate: where c gd is the total capacitance between gate and drain of the external fet. current limit and the capac- itive load at the drain control the slew rate during start- up. during current-limit regulation, the max5945 manipulates the gate_ voltage to control the voltage at sense_. a fast pulldown activates if sense_ over- shoots the limit threshold. the fast pulldown current increases with the amount of overshoot. the maximum fast pulldown current is 100ma. during turn-off, when the gate voltage reaches a value lower than 1.2v, a strong pulldown switch is activated to keep the fet securely off. digital logic v dd supplies power for the internal logic circuitry. v dd ranges from +1.71v to +3.7v and determines the logic thresholds for the cmos connections (sdain, sdaout, scl, auto, shd_ , a_). this voltage range enables the max5945 to interface with a nonisolated low-voltage microcontroller. the max5945 checks the digital supply for compatibility with the internal logic. the max5945 also features a v dd undervoltage lockout (v dduvlo ) of +1.35v. a v dduvlo condition keeps the max5945 in reset and the ports shut off. bit 0 in the supply event register shows the status of v dduvlo (table 11) after v dd has recovered. all logic inputs and outputs reference to dgnd. dgnd and agnd are completely isolated internally to the max5945. in a completely isolated system, the digital signal can be referenced indifferently to v agnd or v ee or at voltages even higher than agnd (up to 60v). v dd - v dgnd must be greater than 3.0v when v dgnd (v ee + 3.0v) when using the ac disconnect detection feature, agnd must be connected directly to dgnd and v dd must be greater than +3v. in this configuration, con- nect dgnd to agnd at a single point in the system as close to max5945 as possible. hardware shutdown shd_ shuts down the respective ports without using the serial interface. hardware shutdown offers an emer- gency turn-off feature that allows a fast disconnect of the power supply from the port. pull shd_ low to remove power. interrupt the max5945 contains an open-drain logic output ( int ) that goes low when an interrupt condition exists. r00h and r01h (tables 5 and 6) contain the definitions of the interrupt registers. the mask register r01h determines events that trigger an interrupt. as a response to an interrupt, the controller reads the status of the event reg- ister to determine the cause of the interrupt and takes subsequent actions. each interrupt event register also contains a clear-on-read (cor) register. reading through the cor register address clears the interrupt. int remains low when reading the interrupt through the read-only addresses. for example, to clear a startup fault on port 4 read address 09h (see table 10). use the global pushbutton bit on register 1ah (bit 7, table 22) to clear interrupts, or use a software or hardware reset. undervoltage and overvoltage protection the max5945 contains several undervoltage and over- voltage protection features. table 11 in the register map and description section shows a detailed list of the undervoltage and overvoltage protection features. an internal v ee undervoltage lockout (v eeuvlo ) circuit keeps the mosfet off and the max5945 in reset until v agnd - v ee exceeds 29v for more than 3ms. an internal v ee overvoltage (v ee_ov ) circuit shuts down the ports when (v agnd - v ee ) exceeds 60v. the digital supply also contains an undervoltage lockout (v dduvlo ). ? ? v t i c out gate gd = max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 17 figure 4. foldback current characteristics 50v 30v v su_lim v su_lim / 3 (v sense_ - v ee ) (v out_ - v ee )
max5945 the max5945 also features three other undervoltage and overvoltage interrupts: v ee undervoltage interrupt (v eeuv ), v dd undervoltage interrupt (v dduv ), and v dd overvoltage interrupt (v ddov ). a fault latches into the supply events register (table 11) but the max5945 does not shut down the ports with a v eeuv , v dduv , or v ddov . dc disconnect monitoring setting r13h[dcd_en_] bits high enable dc load mon- itoring during a normal powered state. if sense_ falls below the dc load disconnect threshold, v dcth , for more than t disc , the device turns off power and asserts the ld_disc_ bit of the corresponding port. t disc is programmable using r16h[0-1] and r27h[0-3]. ac disconnect monitoring the max5945 features ac load disconnect monitoring. connect an external sine wave to osc_in. the oscilla- tor requirements are: frequency x v p-p = 200v p-p x hz ?5% positive peak voltage > +2v frequency > 60hz a 100hz ?0%, 2v p-p ?%, with +1.2v offset (v peak = +2.2v, typ) is recommended. the max5945 buffers and amplifies 3x the external oscillator signal and sends the signal to det_, where the sine wave is ac coupled to the output. the max5945 senses the presence of the load by monitor- ing the amplitude of the ac current returned to det_ (see the functional diagram ). setting r13h[acd_en_] bits high enable ac load dis- connect monitoring during the normal powered state. if the ac current peak at the det_ pin falls below i acth for more than t disc , the device turns off power and asserts the ld_disc_ bit of the corresponding port. i acth is programmable using r23h[0-3]. an internal comparator checks for a proper amplitude of the oscillator input. if the positive peak of the input sinusoid falls below a safety value of 2v, osc_fail sets and the port shuts down. power cannot be applied to the ports when acd_en is set high and osc_fail is set high. leave osc_in unconnected or connect it to dgnd when not using ac disconnect detection. when using the ac disconnect detection feature, con- nect agnd directly to dngd as close as possible to the ic. the max5945 also requires a v dd of greater than +3v for this function. see the typical application circuit with ac disconnect for other external compo- nent requirements. thermal shutdown if the max5945 die temperature reaches +150?, an overtemperature fault generates and the max5945 shuts down and the mosfets turn off. the die temper- ature of the max5945 must cool down below +130? to remove the overtemperature fault condition. after a thermal shutdown, the part is reset. address inputs a3, a2, a1, and a0 represent the four lsbs of the chip address, the complete 7-bit chip address (see table 3). the four lsbs latch on the low-to-high transition of reset or after a power-supply start (either on v dd or v ee ). address inputs default high through an internal 50k ? pullup resistor to v dd . the max5945 also responds to the call through a global address 60h (see the global addressing and alert response protocol section). i 2 c-compatible serial interface the max5945 operates as a slave that sends and receives data through an i 2 c-compatible, 2-wire or 3- wire interface. the interface uses a serial data input line (sdain), a serial data output line (sdaout), and a ser- ial clock line (scl) to achieve bidirectional communica- tion between master(s) and slave(s). a master (typically a microcontroller) initiates all data transfers to and from the max5945, and generates the scl clock that syn- chronizes the data transfer. in most applications, con- nect the sdain and the sdaout lines together to form the serial data line (sda). using the separate input and output data lines allows optocoupling with the controller bus when an isolated supply powers the microcontroller. the max5945 sdain line operates as an input. the max5945 sdaout operates as an open-drain output. a pullup resistor, typically 4.7k ? , is required on sdaout. the max5945 scl line operates only as an input. a pullup resistor, typically 4.7k ? , is required on scl if there are multiple masters, or if the master in a single-master system has an open-drain scl output. serial addressing each transmission consists of a start condition (figure 7) sent by a master, followed by the max5945 7-bit slave address plus r/ w bit, a register address byte, one or more data bytes, and finally a stop condition. quad network power controller for power-over-lan 18 ______________________________________________________________________________________ 010 a3 a2 a1 a0 r/w table 3. max5945 address
start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmis- sion with a start (s) condition by transitioning sda from high to low while scl is high. when the master fin- ishes communicating with the slave, the master issues a stop (p) condition by transitioning sda from low to high while scl is high. the stop condition frees the bus for another transmission. max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 19 figure 5. 2-wire serial interface timing details scl sdain t low t high t r t f t buf start condition stop condition repeated start condition start condition t hd, sta t su, dat t hd, dat t su, sta t hd, sta t su, sto figure 6. 3-wire serial interface timing details scl sdain/sda t low t high t r t f t buf start condition stop condition repeated start condition start condition t hd, sta t su, dat t hd, dat t su, sta t hd, sta t su, sto figure 8. bit transfer sda scl data line stable; data valid . change of data allowed figure 7. start and stop conditions start stop sp sda/ sdain scl
max5945 bit transfer each clock pulse transfers one data bit (figure 8). the data on sda must remain stable while scl is high. acknowledge the acknowledge bit is a clocked 9th bit (figure 9), which the recipient uses as a handshake receipt of each byte of data. thus each byte effectively transferred requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda (or the sdaout in the 3-wire interface) during the acknowledge clock pulse, so the sda line is stable low during the high peri- od of the clock pulse. when the master transmits to the max5945, the max5945 generates the acknowledge bit. when the max5945 transmits to the master, the master generates the acknowledge bit. slave address the max5945 has a 7-bit long slave address (figure 10). the bit following the 7-bit slave address (bit eight) is the r/ w bit, which is low for a write command and high for a read command. 010 always represent the first three bits (msbs) of the max5945 slave address. slave address bits a3, a2, a1, and a0 represent the states of the max5945? a3, a2, a1, and a0 inputs, allowing up to sixteen max5945 devices to share the bus. the states of the a3, a2, a1, and a0 latch in upon the reset of the max5945 into reg- ister r11h. the max5945 monitors the bus continuous- ly, waiting for a start condition followed by the max5945? slave address. when the max5945 recog- nizes its slave address, it acknowledges and is then ready for continued communication. global addressing and alert response protocol the global address call is used in writing mode to write the same register to multiple devices (address 0x60). in read mode (address 0x61), the global address call is used as the alert response address. when responding to a global call, the max5945 puts out on the data line its own address whenever its interrupt is active and so does every other device connected to the sdaout line that has an active interrupt. after every bit is transmitted, the max5945 checks that the data line effectively corre- sponds to the data it is delivering. if it is not, it then backs off and frees the data line. this litigation protocol always allows the part with the lowest address to complete the transmission. the microcontroller can then respond to the interrupt and take proper actions. the max5945 does not reset its own interrupt at the end of the alert response protocol. the microcontroller has to do it by clearing the event register through their cor addresses or activating the clr_int pushbutton. quad network power controller for power-over-lan 20 ______________________________________________________________________________________ figure 9. acknowledge scl sda by transmitter clock pulse for acknowledgement start condition sda by receiver 12 89 s figure 10. slave address sda scl 1 0 a3 a2 a1 a0 0 msb lsb ack r/w
message format for writing the max5945 a write to the max5945 comprises of the max5945? slave address transmission with the r/ w bit set to 0, fol- lowed by at least one byte of information. the first byte of information is the command byte (figure 11). the command byte determines which register of the max5945 is written to by the next byte, if received. if the max5945 detects a stop condition after receiving the command byte, then the max5945 takes no further action beyond storing the command byte. any bytes received after the command byte are data bytes. the first data byte goes into the internal register of the max5945 selected by the command byte. if the max5945 transmits multiple data bytes before the max5945 detects a stop condition, these bytes store in subsequent max5945 internal registers because the control byte address auto-increments. any bytes received after the control byte are data bytes. the first data byte goes into the internal register of the max5945 selected by the control byte (figure 8). if multiple data bytes are transmitted before a stop condition is detected, these bytes are stored in subse- quent max5945 internal registers because the control byte address auto-increments. max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 21 figure 11. control byte received saap 0 slave address control byte acknowledge from max5945 acknowledge from max5945 d15 d14 d13 d12 d11 d10 d9 d8 control byte is stored on receipt of stop condition r/w figure 12. control and single data byte received saaap 0 slave address control byte data byte acknowledge from max5945 1 byte auto-increment memory word address d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 how control byte and data byte map into the register acknowledge from max5945 acknowledge from max5945 r/w figure 13. ??data bytes received saaap 0 slave address control byte data byte acknowledge from max5945 n bytes auto-increment memory word address d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 how control byte and data byte map into the register acknowledge from max5945 acknowledge from max5945 r/w
max5945 message format for reading the max5945 reads using the max5945? internally stored command byte as an address pointer, the same way the stored command byte is used as an address pointer for a write. the pointer auto-increments after reading each data byte using the same rules as for a write. thus, a read is initiated by first configuring the max5945? command byte by performing a write (figure 12). the master now reads ??consecutive bytes from the max5945, with the first data byte read from the register addressed by the initialized command byte (figure 13). when performing read-after-write veri- fication, remember to reset the command byte? address because the stored control byte address auto- increments after the write. operation with multiple masters when the max5945 operates on a 2-wire interface with multiple masters, a master reading the max5945 should use repeated starts between the write that sets the max5945? address pointer, and the read(s) that takes the data from the location(s). it is possible for master 2 to take over the bus after master 1 has set up the max5945? address pointer but before master 1 has read the data. if master 2 subsequently resets the max5945? address pointer then master 1? read may be from an unexpected location. command address auto-incrementing address auto-incrementing allows the max5945 to be configured with fewer transmissions by minimizing the number of times the command address needs to be sent. the command address stored in the max5945 generally increments after each data byte is written or read (table 4). the max5945 is designed to prevent overwrites on unavailable register addresses and unin- tentional wrap-around of addresses. register map and description the interrupt register (table 5) summarizes the event register status and is used to send an interrupt signal ( int goes low) to the controller. writing a 1 to r1ah[7] clears all interrupt and events registers. a reset sets r00h to 00h. int_en (r17h[7]) is a global interrupt mask (table 6). the mask_ bits activate the corresponding interrupt bits in register r00h. writing a 0 to int_en (r17h[7]) disables the int output. a reset sets r01h to aaa00a00b, where a is the state of the auto input prior to the reset. the power event register (table 7) r ecords changes in the power status of the four ports. any change in pgood_ (r10h[7:4]) sets pg_chg_ to 1. any change in the pwr_en_ (r10h[3:0]) sets pwen_chg_ to 1. pg_chg_ and pwen_chg_ trigger on the edges of pgood_ and pwr_en_ and do not depend on the actual level of the bits. the power event register has two addresses. when read through the r02h address, the content of the register is left unchanged. when read through the cor r03h address, the register content will be cleared. a reset sets r02h/r03h = 00h. det_end_/cl_end_ is set high whenever detection/ classification is completed on the corresponding port. a 1 in any of the cl_end_ bits forces r00h[4] to 1. a 1 in any of the det_end_ bits forces r00h[3] to 1. as with any other events register, the detect event register (table 8) has two addresses. when read through the r04h address, the content of the register is left unchanged. when read through the cor r05h address, the register content will be cleared. a reset sets r04h/r05h = 00h. ld_disc_ is set high whenever the corresponding port shuts down due to detection of load removal. imax_flt_ is set high when the port shuts down due to an extended overcurrent event after a successful start- up. a 1 in any of the ld_disc_ bits forces r00h[2] to 1. a 1 in any of the imax_flt_ bits forces r00h[5] to 1. as with any of the other events register, the fault event register (table 9) has two add resses. when read through the r06h address, the content of the register is left unchanged. when read through the cor r07h address, the register content will be cleared. a reset sets r06h/r07h = 00h. quad network power controller for power-over-lan 22 ______________________________________________________________________________________ command byte address range auto-increment behavior 0x00 to 0x26 command address will auto- increment after byte read or written 0x26 command address remains at 0x26 after byte written or read table 4. auto-increment rules
max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 23 address = 00h symbol bit r/w description sup_flt 7r interrupt signal for supply faults. sup_flt is the logic or of all the bits [7:0] in register r0ah/r0bh (table 8). tstr_flt 6r interrupt signal for startup failures. tsrt_flt is the logic or of bits [7:0] in register r08h/r09h (table 7). imax_flt 5r interrupt signal for current-limit violations. imax_flt is the logic or of bits [3:0] in register r06h/r07h (table 6). cl_end 4r interrupt signal for completion of classification. cl_end is the logic or of bits [7:4] in register r04h/r05h (table 5) det_end 3r interrupt signal for completion of detection. det_end is the logic or of bits [3:0] in register r04h/r05h (table 5). ld_disc 2r interrupt signal for load disconnection. ld_disc is the logic or of bits [7:4] in register r06h/r07h (table 6). pg_int 1 r interrupt signal for pgood status change. pg_int is the logic or of bits [7:4] in register r02h/r03h (table 4). pe_int 0 r interrupt signal for power-enable status change. pen_int is the logic or of bits [3:0] in register r02h/r03h (table 4). table 5. interrupt register address = 01h symbol bit r/w description mask7 7 r/w interrupt mask bit 7. a logic high enables the sup_flt interrupts. a logic low disables the sup_flt interrupts. mask6 6 r/w interrupt mask bit 6. a logic high enables the tstr_flt interrupts. a low disables the tstr_flt interrupts. mask5 5 r/w interrupt mask bit 5. a logic high enables the imax_flt interrupts. a logic low disables the imax_flt interrupts. mask4 4 r/w interrupt mask bit 4. a logic high enables the cl_end interrupts. a logic low disables the cl_end interrupts. mask3 3 r/w interrupt mask bit 3. a logic high enables the det_end interrupts. a logic low disables the det_end interrupts. mask2 2 r/w interrupt mask bit 2. a logic high enables the ld_disc interrupts. a logic low disables the ld_disc interrupts. mask1 1 r/w interrupt mask bit 1. a logic high enables the pg_int interrupts. a logic low disables the pg_int interrupts. mask0 0 r/w interrupt mask bit 0. a logic high enables the pen_int interrupts. a logic low disables the pen_int interrupts. table 6. interrupt mask register
max5945 quad network power controller for power-over-lan 24 ______________________________________________________________________________________ address = 02h 03h symbol bit r/w r/w description pg_chg4 7 r cor pgood change event for port 4 pg_chg3 6 r cor pgood change event for port 3 pg_chg2 5 r cor pgood change event for port 2 pg_chg1 4 r cor pgood change event for port 1 pwen_chg4 3 r cor power enable change event for port 4 pwen_chg3 2 r cor power enable change event for port 3 pwen_chg2 1 r cor power enable change event for port 2 pwen_chg1 0 r cor power enable change event for port 1 table 7. power event register address = 06h 07h symbol bit r/w r/w description ld_disc4 7 r cor disconnect on port 4 ld_disc3 6 r cor disconnect on port 3 ld_disc2 5 r cor disconnect on port 2 ld_disc1 4 r cor disconnect on port 1 imax_flt4 3 r cor overcurrent on port 4 imax_flt3 2 r cor overcurrent on port 3 imax_flt2 1 r cor overcurrent on port 2 imax_flt1 0 r cor overcurrent on port 1 table 9. fault event register address = 04h 05h symbol bit r/w r/w description cl_end4 7 r cor classification completed on port 4 cl_end3 6 r cor classification completed on port 3 cl_end2 5 r cor classification completed on port 2 cl_end1 4 r cor classification completed on port 1 det_end4 3 r cor detection completed on port 4 det_end3 2 r cor detection completed on port 3 det_end2 1 r cor detection completed on port 2 det_end1 0 r cor detection completed on port 1 table 8. detect event register
if the port remains in current limit or the pgood condi- tion is not met at the end of the startup period, the port shuts down and the corresponding strt_flt_ is set to 1. a 1 in any of the strt_flt_ bits forces r00h[6] to 1. ivc_ is set to 1 whenever the port current exceeds the maximum allowed limit for the class (determined during the classification process). a 1 in any of ivc_ forces r00h[6] to 1. when the cl_disc (r17h[2]) is set to 1, the port will also limit the load current according to its class as specified in the electrical characteristics table. as with any other events register, the startup event register (table 10) has two addresses. when read through the r08h address, the content of the reg- ister is left unchanged. when read through the cor r09h address, the register content will be cleared. a reset sets r08h/r09h = 00h. the max5945 continuously monitors the power supplies and sets the appropriate bits in the supply event register (table 11). v dd_ov / v ee_ov is set to 1 whenever v dd / v ee exceeds its overvoltage threshold. v dd_uv / v ee_uv is set to 1 whenever v dd / v ee falls below its undervolt- age threshold. osc_fail is set to 1 whenever the amplitude of the oscillator signal at the osc_input falls below a level that might compromise the ac disconnect detection max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 25 address = 08h 09h symbol bit r/w r/w description ivc4 7 r cor class overcurrent flag for port 4 ivc3 6 r cor class overcurrent flag for port 3 ivc2 5 r cor class overcurrent flag for port 2 ivc1 4 r cor class overcurrent flag for port 1 strt_flt4 3 r cor startup failed on port 4 strt_flt3 2 r cor startup failed on port 3 strt_flt2 1 r cor startup failed on port 2 strt_flt1 0 r cor startup failed on port 1 table 10. startup event register address = 0ah 0bh symbol bit r/w r/w description tsd 7 r cor overtemperature shutdown v dd_ov 6 r cor v dd overvoltage condition v dd_uv 5 r cor v dd undervoltage condition v ee_uvlo 4 r cor v ee undervoltage lockout condition v ee_ov 3 r cor v ee overvoltage condition v ee_uv 2 r cor v ee undervoltage condition osc_fail 1 r cor oscillator amplitude is below limit v dd_uvlo 0 r cor v dd undervoltage lockout condition table 11. supply event register address = 0ch, 0dh, 0eh, 0fh symbol bit r/w description reserved 7 r reserved 6 r class_[2] 5 r class_[1] class_ 4 r class_[0] reserved 3 r reserved 2 r det_[2] 1 r det_[1] det_st_ 0 r det_[0] table 12. port status registers
max5945 function. osc_fail generates an interrupt only if at least one of the acd_en (r13h[7:4]) bits is set high. a thermal-shutdown circuit monitors the temperature of the die and resets the max5945 if the temperature exceeds +150?. tsd is set to 1 after the max5945 returns to normal operation. tsd is also set to 1 after every uvlo reset. when v dd and/or |v ee | is below its undervoltage lock- out (uvlo) threshold, the max5945 is in reset mode and securely holds all ports off. when v dd and |v ee | rise to above their respective uvlo thresholds, the device comes out of reset as soon as the last supply crosses the uvlo threshold. the last supply corre- sponding uv and uvlo bits in the supply event regis- ter will be set to 1. a 1 in any supply event register? bits forces r00h[7] to 1. as with any other events register, the supply event register has two addresses. when read through the r0ah address, the content of the register is left unchanged. when read through the cor r0bh address, the register content will be cleared. a reset sets r0ah/r0bh to 00100001 if v dd comes up after v ee or to 00010100 if v ee comes up after v dd . the port status register (table 12) records the results of the detection and classification at the end of each phase in three encoding bits each. r0ch contains detection and classification status of port 1. r0dh corresponds to port 2, r0eh corresponds to port 3 and r0fh corresponds to port 4. tables 12a and 12b show the detection/classifica- tion result decoding charts, respectively. as a protection, when poff_cl (r17h[3], table 20) is set to 1, the max5945 prohibits turning on power to the port that returns a status 111 after classification. a reset sets 0ch, 0dh, 0eh, and 0fh = 00h. pgood_ is set to 1 (table 13) at the end of the power-up startup period if the power-good condition is met (0 < (v out - v ee) < pg th ). the power-good condition must remain valid for more than t pgood to assert pgood_. pgood_ is reset to 0 whenever the output falls out of the power-good condition. a fault condition immediately forces pgood_ low. pwr_en_ is set to 1 when the port power is turned on. pwr_en_ resets to 0 as soon as the port turns off. any transition of pgood_ and pwr_en_ bits set the corre- sponding bit in the power event registers r02h/r03h (table 7). a reset sets r10h = 00h. a3, a2, a1, a0 (table 14) represent the four lsbs of the max5945 address (table 3). during a reset, the device latches into r11h. these four bits address from the cor- responding inputs as well as the state of the midspan and auto inputs. changes to those inputs during nor- mal operation are ignored. the max5945 uses two bits for each port to set the mode of operation (table 15). set the modes according to table 15a. a reset sets r12h = aaaaaaaa where a represents the latched-in state of the auto input prior to the reset. use software to change the mode of operation. quad network power controller for power-over-lan 26 ______________________________________________________________________________________ det_st_[2:0] detected description 000 none detection status unknown 001 dcp positive dc supply connected at the port (agnd - v out_ < 1.65v) 010 high cap high capacitance at the port (>5?) 011 rlow low resistance at the port. r pd < 17k ? . 100 det_ok detection pass. 17k ? > r pd > 28k ? . 101 rhigh high resistance at the port. r pd > 28k ? . 110 open0 open port (i < 12.5?) 111 dcn negative dc supply connected to the port (v out - v ee < 2v) table 12a. detection result decoding chart class_[2:0] class result 000 unknown 001 1 010 2 011 3 100 4 101 undefined (treated as class 0) 110 0 111 current limit (>i cilim ) table 12b. classification result decoding chart
software resets of ports (reset_p_ bit, table 22) do not affect the mode register. setting dcd_en_ to 1 enables the dc load disconnect detection feature (table 16). setting acd_en_ to 1 enables the ac load disconnect feature. if enabled, the load disconnect detection starts during power mode and after startup when the corresponding pgood_ bit in register r10h (table 13) goes high. a reset sets r13h = 0000aaaa where a represents the latched-in state of the auto input prior to the reset. setting det_en_/class_en_ to 1 (table 17) enables load detection/classification, respectively. detection always has priority over classification. to perform clas- sification without detection, set the det_en_ bit low and class_en_ bit high. max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 27 address = 10h symbol bit r/w description pgood4 7r power-good condition on port 4 pgood3 6r power-good condition on port 3 pgood2 5r power-good condition on port 2 pgood1 4r power-good condition on port 1 pwr_en4 3r power is enabled on port 4 pwr_en3 2r power is enabled on port 3 pwr_en2 1r power is enabled on port 2 pwr_en1 0r power is enabled on port 1 table 13. power status register address = 11h symbol bit r/w description reserved 7r reserved reserved 6r reserved a3 5r device address, a3 pin latched-in status a2 4r device address, a2 pin latched-in status a1 3r device address, a1 pin latched-in status a0 2r device address, a0 pin latched-in status midspan 1r midspan input? latched-in status auto 0r auto input? latched-in status table 14. address input status register address = 12h symbol bit r/w description p4_m1 7 r/w m0de[1] for port 4 p4_m0 6 r/w m0de[0] for port 4 p3_m1 5 r/w m0de[1] for port 3 p3_m0 4 r/w m0de[0] for port 3 p2_m1 3 r/w m0de[1] for port 2 p2_m0 2 r/w m0de[0] for port 2 p1_m1 1 r/w m0de[1] for port 1 p1_m0 0 r/w m0de[0] for port 1 table 15. mode register
max5945 in manual mode, r14h works like a pushbutton. set the bits high to begin the corresponding routine. the bit clears after the routine finishes. when entering auto mode, r14h defaults to ffh. when entering manual mode, r14h defaults to 00h. when entering semi mode, r1h is left unchanged but it is reset every time the software commands power off the port. a reset or power-up sets r14h = aaaaaaaab where a represents the latched-in state of the auto input prior to the reset. setting bckoff_ to 1 (table 18) enables cadence timing on each port where the port backs off and waits 2.2s after each failed load discovery detection. the ieee 802.3af standard requires a pse that delivers power through the spare pairs (midspan pse) to have cadence timing. a reset sets r14h = 0000xxxx where x is the logic and of the midspan and auto input state prior to a reset. bckoff_ can be changed by software at any time while changes to the midspan and auto input state during normal operation are ignored. tstart[1,0] (table 19) programs the startup timers, startup time is the time the port is allowed to be in current limit during startup. tfault_[1,0] programs the fault time. fault time is the time allowable for the port to be in current limit during normal operation. rstr[1,0] pro- grams the discharge rate of the tfault_ counter and effectively sets the time the port remains off after an over- current fault. tdisc[1,0] programs the load disconnect detection time. the device turns off power to the port if it fails to provide a minimum power maintenance signal for longer than the load disconnect detection time (tdisc). set the bits in r16h to scale the tstart, tfault, and tdisc to a multiple of their nominal value specified in the electrical characteristics table. r27h and r28h fur- quad network power controller for power-over-lan 28 ______________________________________________________________________________________ mode description 00 shutdown 01 manual 10 semi auto 11 auto table 15a. mode status address = 13h symbol bit r/w description acd_en4 7 r/w enable ac disconnect detection on port 4 acd_en3 6 r/w enable ac disconnect detection on port 3 acd_en2 5 r/w enable ac disconnect detection on port 2 acd_en1 4 r/w enable ac disconnect detection on port 1 dcd_en4 3 r/w enable dc disconnect detection on port 4 dcd_en3 2 r/w enable dc disconnect detection on port 3 dcd_en2 1 r/w enable dc disconnect detection on port 2 dcd_en1 0 r/w enable dc disconnect detection on port 1 table 16. load disconnect detection enable register address = 14h symbol bit r/w description class_en4 7 r/w enable classification on port 4 class_en3 6 r/w enable classification on port 3 class_en4 5 r/w enable classification on port 2 class_en3 4 r/w enable classification on port 1 det_en4 3 r/w enable detection on port 4 det_en3 2 r/w enable detection on port 3 det_en2 1 r/w enable detection on port 2 det_en1 0 r/w enable detection on port 1 table 17. detection and classification enable register
ther extend the programming range of these timers and also increase the programming resolution. when the max5945 shuts down a port due to an extended overcurrent condition (either during startup or normal operation), if rsrt_en is set high, then the part does not allow the port to power back on before the restart timer (table 19a) returns to zero. this effectively sets a minimum duty cycle that protects the external mosfet from overheating during prolonged output overcurrent conditions. a reset sets r16h = 00h. setting cl_disc to 1 (table 20) enables port-over- class current protection, where the max5945 scales down the overcurrent limit (v flt_lim ) according to the port classification status. this feature provides protec- tion to the system against pds that violate their maxi- mum class current allowance. a reset sets r17h = 0xc0. power-enable pushbutton (table 21) for semi and manual modes. setting pwr_on_ to 1 turns on power to the corresponding port. setting pwr_off_ to 1 turns off power to the port. pwr_on_ is ignored max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 29 address = 15h symbol bit r/w description reserved 7 r reserved reserved 6 r reserved reserved 5 r reserved reserved 4 r reserved bckoff4 3 r/w enable cadence timing on port 4 bckoff3 2 r/w enable cadence timing on port 3 bckoff2 1 r/w enable cadence timing on port 2 bckoff1 0 r/w enable cadence timing on port 1 table 18. backoff enable register address = 16h symbol bit r/w description rstr[1] 7 r/w restart timer programming bit 1 rstr[0] 6 r/w restart timer programming bit 0 tstart[1] 5 r/w startup timer programming bit 1 tstart[0] 4 r/w startup timer programming bit 0 tfault[1] 3 r/w overcurrent timer programming bit 1 tfault[0] 2 r/w overcurrent timer programming bit 0 tdisc[1] 1 r/w load disconnect timer programming bit 1 tdisc[0] 0 r/w load disconnect timer programming bit 0 table 19. timing register bit [1:0] rstr t disc t start t fault 00 16 x t fault t disc nominal (350ms, typ) t start nominal (60ms, typ) t fault nominal (60ms, typ) 01 32 x t fault 1/4 x t disc nominal 1/2 x t start nominal 1/2 x t fault nominal 10 64 x t fault 1/2 x t disc nominal 2 x t start nominal 2 x t fault nominal 11 0 x t fault 2 x t disc nominal 4 x t start nominal 4 x t fault nominal table 19a. startup, fault, and load disconnect timers with default values in the register 27h and 28h
max5945 when the port is already powered and during shut- down. pwr_off_ is ignored when the port is already off and during shutdown. after execution, the bits reset to 0. during detection or classification, if pwr_on_ goes high, the max5945 gracefully terminates the cur- rent operation and turn-on power to the port. the max5945 ignores the pwr_on_ in auto mode. a reset sets r19h = 00h. quad network power controller for power-over-lan 30 ______________________________________________________________________________________ address = 17h symbol bit r/w description int_en 7 r/w a logic high enables int functionality rstr_en 6r a logic high enables the autorestart protection time off (as set by the rsrt[1:0] bits) reserved 5r reserved reserved 4r reserved poff_cl 3r a l og i c hi g h p r events p ow er - up after a cl assi fi cati on fai l ur e ( i > 50m a, val i d onl y i n au to m od e) cl_disc 2 r/w a logic high enables reduced current-limit voltage threshold (v flt_lim ) according to port classification result reserved 1 r/w reserved reserved 0 r/w reserved table 20. miscellaneous configurations address = 19h symbol bit r/w description pwr_off4 7w a logic high powers off port 4 pwr_off3 6w a logic high powers off port 3 pwr_off2 5w a logic high powers off port 2 pwr_off1 4w a logic high powers off port 1 pwr_on4 3w a logic high powers on port 4 pwr_on3 2w a logic high powers on port 3 pwr_on2 1w a logic high powers on port 2 pwr_on1 0w a logic high powers on port 1 table 21. power enable pushbuttons address = 1ah symbol bit r/w description clr_int 7 w a logic high clears all interrupts reserved 6 reserved reserved 5 reserved reset_ic 4 w a logic high resets the max5945 reset_p4 3 w a logic high softly resets port 4 reset_p3 2 w a logic high softly resets port 3 reset_p2 1 w a logic high softly resets port 2 reset_p1 0 w a logic high softly resets port 1 table 22. global pushbuttons
writing a 1 to clr_int (table 22) clears all the event registers and the corresponding interrupt bits in register r00h. writing a 1 to reset_p_ turns off power to the cor- responding port and resets only the status and event registers of that port. after execution, the bits reset to 0. writing a 1 to reset_ic causes a global software reset, after which the register map is set back to its reset state. a reset sets r1ah = 00h. enable smode function (table 24) by setting en_whdog (r1fh[7]) to 1. smode_ bit goes high when the watchdog counter reaches zero and the port(s) switch over to hardware-controlled mode. smode_ also goes high each and every time the software tries to power-on a port but is denied since the port is in hard- ware mode. a reset sets r1ch = 00h. set en_whdog (r1fh[7]) to 1 (t able 25) to enable the watchdog function. when activated, the watchdog timer counter, wdtime[7:0], continuously decrements toward zero once every 164ms. once the counter reaches zero (also called watchdog expiry), the max5945 enters hard- ware-controlled mode and each port shifts to a mode set by the hwmode_ bit in register r1fh ( table 24). use software to set wdtime and continuously set this register to some non-zero value before the register reaches zero to prevent a watchdog expiry. in this way, the software gracefully manages the power to ports upon a system crash or switchover. while in hardware-controlled mode, the max5945 ignores all requests to turn the power on and the flag smode_ indicates that the hardware took control of the max5945 operation. in addition, the software is not allowed to change the mode of operation in hardware- controlled mode. a reset sets r1eh = 00h. setting en_whdog (table 26) high activates the watchdog counter. when the counter reaches zero, the port switches to the hardware-controlled mode deter- mined by the corresponding hwmode_ bit. a low in hwmode_ switches the port into shutdown by setting max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 31 address = 1bh symbol bit r/w description 7r id_code[4] 6r id_code[3] 5r id_code[2] 4r id_code[1] id_code 3r id_code[0] 2r rev [2] 1r rev [1] rev 0r rev [0] table 23. id register id register keeps track of the device id number and revision. the max5945? id_code[4:0] = 11000b. contact the factory for rev[2:0] value. address = 1ch symbol bit cor description reserved 7 reserved reserved 6 reserved reserved 5 reserved reserved 4 reserved smode4 3 cor hardware control flag for port 4 smode3 2 cor hardware control flag for port 3 smode2 1 cor hardware control flag for port 2 smode1 0 cor hardware control flag for port 1 table 24. smode register
max5945 the bits in register r12h to 00. a high in hwmode_ switches the port into auto mode by setting the bits in register r12h to 11. if wd_int_en is set, an interrupt is sent if any of the smode bits are set. a reset sets r1fh = 00h. use igate[2:0] (table 27) to set the gate pin pullup current, i pu , according to the following formula: i pu = 50? - 6.25 x n where n is the decimal value of igate[2:0]. use ac_th[2:0] to program the current threshold of the ac disconnect comparator according to the following formula: iac_th = 213.68? + 28.33? x n where n is the decimal value of ac_th[2:0]. note: the programmed value has the same percent- age tolerance as the value specified in the electrical characteristics . when set low, det_byp inhibits port power-on if the discovery detection was bypassed in auto mode. when set high, it allows the part to turn on power to a non-ieee 802.3af load without doing detection. if oscf_rs is set high, the osc_fail bit is ignored. a reset sets r23h = 04h, which sets i pu = 50? and i ac_th = 325? as shown in the electrical characteristics . use r27h (table 28) to program the current-limit threshold, v su_lim , and the nominal load disconnect detection time, t disc nominal. use imax[3:0] to program the current-limit trip voltage according to the following formula: v su_lim = 135mv + 19.25mv x n where n is the decimal value of imax[3:0]. the v fault_lim limit scales proportionally to the v su_lim value (i fault = 88% of v su_lim ). a reset sets r27h = 47h, which sets v su_lim = 212mv (typical) as shown in the electrical characteristics . the default threshold is set to meet the ieee 802.3af stan- dard when using an r sense = 0.5 ? ?%, 100ppm. quad network power controller for power-over-lan 32 ______________________________________________________________________________________ address = 1eh symbol bit r/w description 7 r/w wdtime[7] 6 r/w wdtime[6] 5 r/w wdtime[5] 4 r/w wdtime[4] 3 r/w wdtime[3] 2 r/w wdtime[2] 1 r/w wdtime[1] wdtime 0 r/w wdtime[0] table 25. watchdog timer register address = 1fh symbol bit r/w description en_whdog 7 r/w a logic high enables the watchdog function wd_int_en 6 enables interrupt on smode_ bits reserved 5 reserved 4 r/w hwmode4 3 r/w port 4 switches to auto if logic high and to shutdown if logic low when watchdog timer expires hwmode3 2 r/w port 3 switches to auto if logic high and to shutdown if logic low when watchdog timer expires hwmode2 1 r/w port 2 switches to auto if logic high and to shutdown if logic low when watchdog timer expires hwmode1 0 r/w port 1 switches to auto if logic high and to shutdown if logic low when watchdog timer expires table 26. switch mode register
use tf_pr[3:0] to set the nominal value for t disc according to the following formula: t disc nominal = 238ms + 16ms x n where n is the decimal value of the binary words tf_pr[3:0]. a reset sets r27h = 47h, which sets t disc nominal = 350ms as shown in the electrical characteristics . use r27h in conjunction with the two tdisc[1:0] bits in reg- ister r16h to program the values of t disc from 60ms to almost 340ms with a 16ms resolution. example: set td_pr[3:0] = 1111b, tdisc[1:0] = 11b then: t disc = 2 x t disc nominal = 2 x (238ms + 16ms x 15) = 956ms note: the programmed value has the same percent- age tolerance as the value specified in the electrical characteristics . max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 33 address = 23h symbol bit r/w description 7 r/w igate[2] 6 r/w igate[1] igate 5 r/w igate[0] det_byp 4 r/w detect bypass protection in auto mode oscf_rs 3 r/w osc_fail reset bit 2 r/w ac_th[2] 1 r/w ac_th[1] ac_th 0 r/w ac_th[0] table 27. program register 1 address = 27h symbol bit r/w description 7 r imax[3]. v su_lim programming bit 3. 6 r imax[2]. v su_lim programming bit 2. 5 r imax[1]. v su_lim programming bit 1. imax 4 r imax[0]. v su_lim programming bit 0. 3 r td_pr[3]. t disc nominal programming bit 3. 2 r td_pr [2]. t disc nominal programming bit 2. 1 r td_pr [1]. t disc nominal programming bit 1. td_pr 0 r td_pr [0]. t disc nominal programming bit 0. table 28. program register 2
max5945 use the program registers (table 29) to set the nominal value for t fault and t start for all ports according to the following formula: t fault nominal = 40.96ms + 2.72ms x n t start nominal = 40.96ms + 2.72ms x n where n is the decimal value of tf_pr[3:0] or ts_pr[3:0], respectively. a reset sets r28h = 77h, which sets t fault = t start = 60ms as shown in the electrical characteristics . use r28h in conjunction with the two tstart and tfault bits in register r16h to program the values of t fault and t start from about 20ms to almost 330ms with a 2.72ms resolution. example: set tf_pr[3:0] = 1111b, tfault[1:0] = 11b then: t fault = 4 x t fault nominal = 4 x (40.96ms + 2.72ms x 15) = 327ms note: the programmed value has the same percent- age tolerance as the value specified in the electrical characteristics . quad network power controller for power-over-lan 34 ______________________________________________________________________________________ address = 28h symbol bit r/w description 7 r tf_pr[3]. t fault nominal programming bit 3. 6 r tf_pr[2]. t fault nominal programming bit 2. 5 r tf_pr[1]. t fault nominal programming bit 1. tf_pr 4 r tf_pr[0]. t fault nominal programming bit 0. 3 r ts_pr[3]. t start nominal programming bit 3. 2 r ts_pr[2]. t start nominal programming bit 2. 1 r ts_pr[1]. t start nominal programming bit 1. ts_pr 0 r ts_pr[0]. t start nominal programming bit 0. table 29. program register 3
max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 35 table 30. register map summary addr register name r/w port bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state interrupts 00h interrupt ro g sup_flt tstr_flt imax_flt cl_end det_end ld_disc pg_int pe_int 0000,0000 01h int mask r/w g mask7 mask6 mask5 mask4 mask3 mask2 mask1 mask0 aaa0,0a00 events 02h power event ro 4321 0000,0000 03h power event cor cor pg_chg4 pg_chg3 pg_chg2 pg_chg1 pwen_ chg4 pwen_ chg3 pwen_ chg2 pwen_ chg1 04h detect event ro 4321 0000,0000 05h detect event cor cor cl_end4 cl_end3 cl_end2 cl_end1 det_end4 det_end3 det_end2 det_end1 06h fault event ro 4321 0000,0000 07h fault event cor cor ld_disc4 ld_disc3 ld_disc2 ld_disc1 imax_flt4 imax_flt3 imax_flt2 imax_flt1 08h tstart event ro 4321 0000,0000 09h tstart event cor cor ivc4 ivc3 ivc2 ivc1 strt_flt4 strt_flt3 strt_flt2 strt_flt1 0ah supply event ro 4321 0011,0101* 0bh supply event cor cor tsd vdd_ov vdd_uv vee uvlo vee_ov vee_uv osc_fail vdd_uvlo status 0ch port 1 status ro 1 reserved class1[2] class1[1] class1[0] reserved det_st1 [2] det_st1 [1] det_st1 [0] 0000,0000 0dh port 2 status ro 2 reserved class2[2] class2[1] class2[0] reserved det_st2 [2] det_st2 [1] det_st2 [0] 0000,0000 0eh port 3 status ro 3 reserved class3[2] class3[1] class3[0] reserved det_st3 [2] det_st3 [1] det_st3 [0] 0000,0000 0fh port 4 status ro 4 reserved class4[2] class4[1] class4[0] reserved det_st4 [2] det_st4 [1] det_st4 [0] 0000,0000 10h power status ro 4321 pgood4 pgood3 pgood2 pgood1 pwr_en4 pwr_en3 pwr_en2 pwr_en1 0000,0000 11h pin status ro g reserved reserved a3 a2 a1 a0 midspan auto 00a3a2, a1a0ma * uv and uvlo bits of v ee and v dd asserted depend on the order v ee and v dd supplies are brought up. a = auto pin state, a3..0 = address pin states, m = midspan pin state, r = contact factory for current revision code table 15a.
max5945 quad network power controller for power-over-lan 36 ______________________________________________________________________________________ table 30. register map summary (continued) addr register name r/w port bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset state configuration 12h operating mode r/w 4321 p4_m1 p4_m0 p3_m1 p3_m0 p2_m1 p2_m0 p1_m1 p1_m0 aaaa,aaaa 13h disconnect enable r/w 4321 acd_en4 acd_en3 acd_en2 acd_en1 dcd_en4 dcd_en3 dcd_en2 dcd_en1 0000,aaaa 14h det/class enable r/w 4321 class_en4 class_en 3 class_en 2 class_en 1 det_en4 det_en3 det_en2 det_en1 aaaa,aaaa 15h backoff enable r/w 4321 reserved reserved reserved reserved bckoff4 bckoff3 bckoff2 bckoff1 0000,mmmm 16h timing config r/w g rstr[1] rstr[0] tstart[1] tstart[0] tfault[1] tfault[0] tdisc[1] tdisc[0] 0000,0000 17h misc config r/w g int_en rstr_en reserved reserved poff_cl cl_disc reserved reserved 1100,0000 pushbuttons 18h reserved r/w g reserved reserved reserved reserved reserved reserved reserved reserved 19h power enable wo 4321 pwr_off4 pwr_off3 pwr_off2 pwr_off1 pwr_on4 pwr_on3 pwr_on2 pwr_on1 0000,0000 1ah global wo g clr_int reserved reserved reset_ic reset_p4 reset_p3 reset_p2 reset_p1 0000,0000 general 1bh id ro g id_code[ 4] id_code[ 3] id_code[ 2] id_code[ 1] id_code[ 0] rev [2] rev [1] rev [0] 1100,0rrr 1ch smode cor 4321 reserved reserved reserved reserved smode4 smode3 smode2 smode1 00000000 1dh reserved g reserved reserved reserved reserved reserved reserved reserved reserved 00000000 1eh watchdog r/w g wdtime[7] wdtime[6] wd ti me [ 5] wdtime[4] wdtime[3] wdtime[2] wdtime[1] wdtime[0] 00000000 1fh switch mode r/w 4321 en_ whdog wd_int_en reserved reserved hwmode4 hwmode3 hwmode2 hwmode1 00000000 maxim reserved 20h reserved g reserved reserved reserved reserved reserved reserved reserved reserved 00000000 21h reserved g reserved reserved reserved reserved reserved reserved reserved reserved 00000000 22h reserved g reserved reserved reserved reserved reserved reserved reserved reserved 00000000 23h program1 r/w 4321 igate[2] igate[1] igate[0] det_byp oscf_rs ac_th[0] ac_th[0] ac_th[0] 00000100 24h reserved g reserved reserved reserved reserved reserved reserved reserved reserved 00000000 25h reserved g reserved reserved reserved reserved reserved reserved reserved reserved 00000000 26h reserved g reserved reserved reserved reserved reserved reserved reserved reserved 00000000 27h program2 r/w g imax[3] imax[2] imax[1] imax[0] td[3] td[2] td[1] td[0] 01000111 28h program3 r/w g tf_pr[3] tf_pr[2] tf_pr[1] tf_pr[0] ts_pr[3] ts_pr[2] ts_pr[1] ts_pr[0] 01110111 * uv and uvlo bits of v ee and v dd asserted depend on the order v ee and v dd supplies are brought up. a = auto pin state, a3..0 = address pin states, m = midspan pin state, r = contact factory for current revision code table 15a.
max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 37 figure 14. poe system block diagram max5945 quad poe controller max5020 -48v to +3.3v dc-dc max5940b pd interface controller max5014 dc-dc converter gnd -48v phy data phy load data power 3.3v -48v power max5941/max5942 pd interface and dc-dc converter or pse (switches/routers, etc) pd (ip phone, wireless access point, security cameras, etc.) rj?5 rj?5 power and data over twisted-pair ethernet cable vout applications information
max5945 quad network power controller for power-over-lan 38 ______________________________________________________________________________________ figure 15. poe system diagram of one complete port, endpoint pse max5945 -48v gate_ internal pulldown (manual mode) 1k ? -48vrtn fdt3612 100v, 120m ? sot-223 sense_ v ee out_ off on det_ sdain sdaout scl dgnd v dd a0 a1 a2 a3 osc_in auto midspan agnd internal pulldown (signal mode) 0.5 ? 1% 1n4448 1k ? 1 of 4 channels 1.8v to 5v, (ref to dgnd) int reset 3k ? 3k ? 180 ? 180 ? 180 ? optional buffer internal 50k ? pullup 4.7k ? 1k ? v dd 1n4002 hpcl063l optional buffer optional buffer hpcl063l hpcl063l vccrtn v cc (3.3v) scl sda serial interface 3k ? 3k ? isolation 0.47 f 100v shd_ sine wave 100hz 10% peak amplitude 2.2v 0.1v valley amplitude 0.2v 0.1v smbj 58ca 0.1 f 2.2m ? -48vout 8 7 5 4 6 3 2 1 -48vout 0.1 f 0.1 f 0.1 f 0.1 f 75 ? 75 ? 75 ? 75 ? 1000pf 250vac 24 22 21 19 23 20 rx1+ rx1- tx1+ tx1- rxt1 txct1 rd1+ rd1- td1+ td1- 1 3 4 5 phy 1/2 of h2005a rj?5 connector
max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 39 figure 16. poe system diagram of one complete port, midspan pse max5945 -48v gate_ internal pulldown (manual mode) 1k ? -48vrtn fdt3612 100v, 120m ? sot-223 sense_ v ee out_ off on det_ sdain sdaout scl dgnd v dd a0 a1 a2 a3 osc_in auto midspan agnd internal pulldown (signal mode) 0.5 ? 1% 1n4448 1k ? 1 of 4 channels 1.8v to 5v (ref to dgnd) int reset 3k ? 3k ? 180 ? 180 ? 180 ? optional buffer internal 50k ? pullup 4.7k ? 1k ? v dd 1n4002 hpcl063l optional buffer optional buffer hpcl063l hpcl063l vccrtn v cc (3.3v) scl sda serial interface 3k ? 3k ? isolation 0.47 f 100v shd_ sine wave 100hz 10% peak amplitude 2.2v 0.1v valley amplitude 0.2v 0.1v smbj 58ca 0.1 f 2.2m ? -48vout 8 7 5 4 6 3 2 1 rj?5 connector -48vout data
max5945 quad network power controller for power-over-lan 40 ______________________________________________________________________________________ figure 17. -48v to +3.3v (300ma) boost converter solution for v dig gnd -48v -48v gnd c6 0.47 f 100v r10 2 ? r6 1 ? c3 15nf q4 mmbta56 r5 1k ? l1 68 h, do3308p-683 max5020 1 2 3 4 8 7 6 5 v+ v dd fb v cc ndrv gnd cs c2 0.022 f r8 30 ? c1 0.1 f c8 2.2 f r4 1 ? r9 1 ? gate source drain q1 si2328 ds c9 4.7 h c7 0.22 f r7 1.02k ? r2 6.81k ? r3 2.61k ? q3 mmbta56 d1 diodes inc.: b1100 c4 220 f sanyo 6sps220m r1 2.6k ? q2 mmbta56 c5 4.7 f +3.3v +3.3v gnd 300ma ss_shdn figure 18. layout example for boost converter solution for v dig 1700 (mils) 965 (mils) 1700 (mils) 965 (mils) 1700 (mils) 965 (mils)
max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 41 designation description c1 0.1?, 25v ceramic capacitor c2 0.022?, 25v ceramic capacitor c3 15nf, 25v ceramic capacitor c4 220? capacitor sanyo 6svpa220maa c5 4.7?, 16v ceramic capacitor c6 0.1?, 100v ceramic capacitor c7 0.22?, 16v ceramic capacitor c8 0.22?, 16v ceramic capacitor c9 4.7nf, 16v ceramic capacitor d1 b1100 100v schottky diode l1 68? inductor coilcraft do3308p-683 or equivalent q1 si2328ds vishay n-channel mosfet, sot23 q2 mmbta56 small-signal pnp q3 mmbta56 small-signal pnp q4 mmbta56 small-signal pnp r1 2.61k ? ?% resistor r2 6.81k ? ?% resistor r3 2.61k ? ?% resistor r4 1 ? ?% resistor r5 1k ? ?% resistor r6 1 ? ?% resistor r7 1.02k ? ?% resistor r8 30 ? ?% resistor r9 1 ? ?% resistor r10 2 ? ?% resistor u1 high-voltage pwm ic max5020esa (8-pin so) component list chip information transistor count: 148,768 process: bicmos
max5945 quad network power controller for power-over-lan 42 ______________________________________________________________________________________ max5945 -48v gate_ internal pulldown (manual mode) 1k ? -48vrtn fdt3612 100v, 120m ? sot-223 sense_ v ee out_ off on det_ sdain sdaout scl dgnd v dd a0 a1 a2 a3 osc_in auto midspan agnd internal pulldown (signal mode) 0.5 ? 1% -48v output to port -48v rtn output to port note: all signal pins are referenced to dgnd. dgnd range is between v ee and (agnd + 4v). 1n4448 1 of 4 channels 1.8v to 3.7v, (ref to dgnd) int reset 3k ? 3k ? 180 ? 180 ? 180 ? optional buffer internal 50k ? pullup 4.7k ? 1k ? v dd can be up to 100k ? hpcl063l optional buffer optional buffer hpcl063l hpcl063l vccrtn v cc (3.3v) scl sda serial interface 3k ? 3k ? isolation n.c. shd_ typical operating circuits typical operating circuit 1 (without ac load removal detection)
max5945 quad network power controller for power-over-lan ______________________________________________________________________________________ 43 max5945 -48v gate_ internal pulldown (manual mode) 1k ? -48vrtn fdt3612 100v, 120m ? sot-223 sense_ v ee out_ off on det_ sdain sdaout scl dgnd v dd a0 a1 a2 a3 osc_in auto midspan agnd internal pulldown (signal mode) 0.5 ? 1% -48v output to port -48v rtn output to port note: all signal pins are referenced to dgnd. 1n4448 1k ? 1 of 4 channels 1.8v to 3.7v, (ref to dgnd) int reset 3k ? 3k ? 180 ? 180 ? 180 ? optional buffer internal 50k ? pullup 4.7k ? 1k ? v dd 1n4002 can be up to 100k ? hpcl063l optional buffer optional buffer hpcl063l hpcl063l vccrtn v cc (3.3v) scl sda serial interface 3k ? 3k ? isolation dgnd must be connected directly to agnd for ac disconnect detection circuit to operate. 0.47 f 100v shd_ sine wave 100hz 10% peak amplitude 2.2v 0.1v valley amplitude 0.2v 0.1v typical operating circuits (continued) typical operating circuit 2 (with ac load removal detection)
max5945 quad network power controller for power-over-lan maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 44 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) ssop.eps package outline, 36l ssop, 0.80 mm pitch 1 1 21-0040 e rev. document control no. approval proprietary information title: front view max 0.011 0.104 0.017 0.299 0.013 inches 0.291 0.009 e c dim 0.012 0.004 b a1 min 0.096 a 0.23 7.40 7.60 0.32 millimeters 0.10 0.30 2.44 min 0.44 0.29 max 2.65 0.040 0.020 l 0.51 1.02 h 0.414 0.398 10.11 10.51 e 0.0315 bsc 0.80 bsc d 0.612 0.598 15.20 15.55 h e a1 a d e b 0 -8 l c top view side view 1 36
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs m axim > p roduc ts > h ot-swap and p ower switc hing max5945 quad network power c ontroller for power-over-lan quickview technical documents ordering info more information all ordering information notes: other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 1. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 2. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 3. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 4. devices: 1-8 of 8 m ax5945 fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max5945c ax 0c to +70c rohs/lead-free: see data sheet max5945c ax+ ssop;36 pin;163 mm dwg: 21-0040e (pdf) use pkgcode/variation: a36mk+4 * 0c to +70c rohs/lead-free: lead free materials analysis max5945c ax+t ssop;36 pin;163 mm dwg: 21-0040e (pdf) use pkgcode/variation: a36mk+4 * 0c to +70c rohs/lead-free: lead free materials analysis max5945c ax-t 0c to +70c rohs/lead-free: see data sheet max5945eax -40c to +85c rohs/lead-free: see data sheet max5945eax-t -40c to +85c rohs/lead-free: see data sheet max5945eax+ -40c to +85c rohs/lead-free: see data sheet max5945eax+t -40c to +85c rohs/lead-free: see data sheet didn't find what you need? next day product selection assistance from applications engineers parametric search applications help quickview technical documents ordering info more information des c ription key features a pplic ations /u s es key spec ific ations diagram data sheet a pplic ation n otes des ign guides e ngineering journals reliability reports software/m odels e valuation kits p ric e and a vailability samples buy o nline p ac kage i nformation lead-free i nformation related p roduc ts n otes and c omments e valuation kits
doc ument ref.: 1 9 -3 4 2 8 ; rev 1 ; 2 0 0 5 -0 9 -1 2 t his page las t modified: 2 0 0 7 -0 8 -0 7 c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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